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ASIC/FPGA Verification Engineer
ASIC/FPGA Verification Engineer
Enfabrica
RemoteOctober 2021 - PresentEnfabrica
Maintain top-level FPGA design and testbench for an FPGA-based network and accelerator memory disaggregator prototype.
Implemented TCP IPv4 NIC packet processor on an FPGA. Took ownership of transit path, which featured header-payload data split functionality, TCP segmentation offload, and TCP header field markup.
Brought up in-house design on Cadence Palladium Emulation platform from scratch. Integrated PCIe and CXL Speed-bridge and Virtual-bridge integration using ICE and IXCOM emulation modes.
Maintained, debugged, and triaged emulation collateral. Interfaced with the software team to successfully perform and deploy HW/SW co-simulation platform. Developed low-level firmware to initialize the chip hardware upon boot up.
https://enfabrica.net/
ASIC Verification Engineer
ASIC Verification Engineer
SpaceX
Irvine, CANovember 2019 - September 2021SpaceX
Verify various RTL design blocks that will make their way into next generation Starlink products: Satellites, Gateways, and User Terminals.
Developed block and system level verification using UVM test harnesses for various ASICs, FPGAs, & Custom IPs. Including verication of a custom RISC-V core.
Took ownership of top-level testbenches for various ASIC and FPGA projects, including block-level verification for custom RISC-V core.
Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
FPGA Engineer
FPGA Engineer
ViaSat
Carlsbad, CAJuly 2018 - November 2019ViaSat
Developed high and low bandwidth peripherals for SoC using RISC-V soft-core processor running Linux.Contributed to an automated build process for Xilinx and Altera targets.
Automate instantiation of custom and vendor specific IP using python and tcl scripts.Implemented hardware accelerated memory test in Verilog, designed to test DDR memory and provide memory diagnostics.
Designed high bandwidth hardware accelerated data generator with AXI streaming interface to test physical data links.
Created JSON test framework for I2C and SPI peripherals that would enable re-usable configuration and automatic transaction generation.
Research Intern
Research Intern
IBM
San Jose, CAJune 2017 - September 2017IBM
Implemented a platform to enable decentralized software distribution for IoT devices using Hyperledger Fabric. Platform would distribute software while ensuring immutability and provenance.
Instructor
Instructor
iD Tech Camps
UCSD, USD, & UCISummer of 2015 & 2016iD Tech Camps
Instructed programming concepts in Scratch, Python, Java, and C++ to 7-17 year olds in groups of 8.
Developed creative and fun lesson plans to illustrate programming problems and paradigms
Computer Science Instructor
Computer Science Instructor
Private Tutor
Irvine, CASeptember 2016 - June 2018Private Tutor
Computer Science instructor for home schooled children. Taught program flow, methods, algorithms, and object-oriented programming in Java and Python.
Build 2D arcade games using Python and PyGame.
Dove into Tkinter GUI development, git version control, and AWS server hosting for socket based multiplayer Battleship game.
Research Assistant
Research Assistant
UCI Research
Irvine, CAJanuary 2017 - May 2018UCI Research
Sequencing the genome of Anopheles Gambiae to find unique differences within the Mopti and Savannah strains, two different species, that are currently in the state of diverging.
Parallelize academic gene sequencing library quickmerge using pthreads in C++, implemented scheduler to maximize sequencing throughput.
Learning Assistant
Learning Assistant
UCI LARC
Irvine, CAOctober 2015 - March 2016UCI LARC
Illustrated problem solving strategies for challenging physics problems to college students. Topics included kinematics and forces in two dimensions.
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